In the design of linear integrated MOS (Metal-Oxide-Semiconductor) circuits, it is often desirable to have an electrical resistance load ("attenuator") element which is linear, that is, where the current through the load is linearly proportional to the voltage across the load over a reasonably wide operating range of voltage. Such a load is particularly useful in connection with such circuits as operational amplifiers and signal filters. However, a straightforward implementation of such a load in the form of a long, resistive path of polycrystalline silicon consumes an inordinately large amount of semiconductor silicon wafer area, typically of the order of several thousand squares of the minimum feature size of the integrated circuit fabrication technique being used; or else such an implementation consumes an unreasonably large amount of power for reasonable voltage drops across such a load. On the other hand, the use of the source to drain resistance of an insulated gate metal-oxide-semiconductor field effect transistor (IGFET or MOSFET) as a load enables more compact implementation of such a load but only at the expense of nonlinearity over desired operating parameters.
It is a known characteristic of a MOSFET that, for somewhat smaller operating signal ranges than desired in linear integrated circuits, this type of transistor can serve as a linear load when operated in the linear region of the "triode region," that is, when the drain to source voltage V.sub.D is well below the "effective gate voltage" V.sub.GE, specifically EQU V.sub.D &lt;&lt;V.sub.GE =V.sub.G -V.sub.TO ( 1)
that is, the drain to source voltage should be kept well below the applied gate to source voltage V.sub.G less the threshold voltage V.sub.TO.
An ideal (perfectly linear) resistor attenuator in a voltage divider configuration (FIG. 1) includes a pair of ideal resistors R.sub.1 and R.sub.2 whose ratio (R.sub.1 /R.sub.2) is selected in accordance with the desired output voltage ##EQU1## where V.sub.IN is the input signal voltage and V.sub.REF is a reference voltage, typically a steady DC voltage. A simple and direct implementation of this ideal resistor attenuator configuration with MOS transistors is illustrated in FIG. 2, using a pair of MOSFETs M.sub.1 and M.sub.2 having transconductances .beta..sub.1 and .beta..sub.2, respectively, where .beta. is proportional to the ratio of the width W to the length L of the transistor channel, as known in the art. The gate electrodes of M.sub.1 and M.sub.2 are connected to a high enough (for N-channel devices) supply voltage V.sub.DD so that operation takes place in both the transistors M.sub.1 and M.sub.2 in the linear portions of their triode regions. However, such an implementation as shown in FIG. 2 suffers from the disadvantage that the input signals must be restricted to an undesirably small range (typically.+-.2 volts for V.sub.DD =20 volts) in order to maintain linearity during operation. This problem of large signal nonlinearity arises from the quadratic term in V.sub.D in the MOSFET drain current relationship in the triode region: EQU I.sub.A =-.beta.[(V.sub.G -V.sub.TO -V.sub.S)(V.sub.D -V.sub.S) -1/2 (V.sub.D -V.sub.S).sup.2 ] (3)
This quadratic term (.beta.V.sub.D.sup.2 /2) becomes appreciable when V.sub.D is not kept well below (V.sub.G -V.sub.TO), that is, when the input signals are large enough to take the operation of the MOSFET out of the linear portion of the triode region. Hence, V.sub.OUT will not be linear in the input signal voltage V.sub.IN for such large signals.
For larger signals, which take the operation out of the linear portion of the triode region, a different approach must thus be taken in order to preserve linearity. One such approach (FIG. 3) uses operation in the saturation regions of the enhancement mode MOS transistors, M.sub.1 and M.sub.2, in which the gate electrode of each such transistor is shorted to its drain by direct ohmic connection. Although the source-drain current now follows a square-law, the attenuator operation is still basically linear, since both transistors have the same type of functional dependence of current on voltage: EQU I.sub.D =-.beta..sub.1 (V.sub.G1 -V.sub.S1 -V.sub.TO)2/2=-.beta..sub.2 (V.sub.G2 -V.sub.S2 -V.sub.TO)2/2 (4)
Accordingly, defining each .beta.=2.alpha..sup.2, it follows that: EQU .alpha..sub.1 (V.sub.G1 -V.sub.S1)=.alpha..sub.2 (V.sub.G2 -V.sub.S1)+(.alpha..sub.1 -.alpha..sub.2)V.sub.TO ( 5)
Since, in the circuit of FIG. 3, V.sub.G1 is the same as V.sub.OUT and V.sub.G2 is the same as V.sub.IN, it is seen that the circuit in FIG. 3 provides a linear attenuator in the voltage divider configuration. However, this circuit becomes highly nonlinear if and when the input signal V.sub.IN swings below the (DC) reference voltage V.sub.REF or even as low as to within two thresholds of V.sub.REF, because then both transistors M.sub.1 and M.sub.2 are turned "off," the functions of drains and sources being reversed. Therefore, the circuit of FIG. 3 undesirably limits the input signal range for linear operation to values of V.sub.IN greater than at least V.sub.REF +2 V.sub.TO.
It would therefore be desirable to have an MOS circuit which provides linear attenuation over a wider range than those of the prior art. By "linear" is meant that the total harmonic distortion for sinusoidal signals of a few volts RMS should be more than about 30 dB below the fundamental.